1. Field of the Invention
The present invention relates to a D/A converter that outputs an analog waveform signal level corresponding to digital waveform signal data. Specifically, the present invention relates to a resistive voltage dividing type D/A converter that divides a reference voltage using a group of serially connected reference resistors in response to a binary code obtained by decoding a digital input signal, to output an analog voltage.
More specifically, the present invention relates to a multi-stage resistive voltage dividing type D/A converter in which a plurality of reference resistor groups are arranged in multiple stages, and particularly, to a multi-stage resistive voltage dividing type D/A converter that eliminates or alleviates influence of the offset voltage of inter-stage output amplifiers caused by a decreased dynamic range.
2. Description of Related Art
In information devices such as computers, a circuit for conversion of a digital signal to an analog signal, i.e., a D/A converter is usually used in order to transmit digitally processed data to a communication channel or output the data in audio or video form.
D/A converters include various types, such as converting circuits using a summing amplifier, resistive voltage dividing type circuits, and current output type circuits. Of these types, the resistive voltage dividing type D/A converter is configured such that a reference voltage using reference resistors is divided in response to a binary code obtained by decoding a digital input signal (see, e.g., Iwao Sagara, “Introduction to A/D and D/A converting circuits, Second Edition” published by Nikkan Kogyo Shimbunsha, Sep. 30, 2004 (pages 268-269)). The reference will be referred to as Non-Patent Reference 1 below. The resistive voltage dividing type D/A converter is satisfactory in its monotonously increasing property and differential nonlinearity, and is thus well adapted to servomechanisms.
The resistive voltage dividing type D/A converter is configured as follows. The circuit has a reference resistor group and an output amplifier, such as an op-amp. In the reference resistor group, a plurality of reference resistors, each having the same resistance value, are serially connected, and across such reference resistor group, a predetermined reference voltage is applied. A divided voltage is extracted from a voltage tap between certain reference resistors of a predetermined N (N=1, 2,. . . ) successive ones of the plurality of reference resistors. The divided voltage is extracted as an analog waveform signal via the output amplifier.
An output terminal is provided via an analog switch at each of nodes between adjacent reference resistors, whereby a voltage tap can be selected by on/off control of the corresponding switch. A digital input signal is decoded, and a voltage tap is determined, and then the analog switch at the determined tap is turned on to extract a divided voltage.
Here, it the analog switch is to be formed only of either a p-channel or n-channel transistor, a linear switching operation cannot be performed over a 0-5V full range required for conversion. To overcome this situation, a D/A converter has been proposed (see, e.g., Japanese Patent Application Publication No. HEI 07-131354 (Patent Reference 1)). In Patent Reference 1, p-channel MOS transistors are used for a high-level output and n-channel MOS transistors are used for a lower-level output, whereby the p-channel and n-channel MOS transistors which are adjacent to each other at the boundary between the respective analog switch groups are set to an equal impedance or conductance, to improve analog output characteristics.
FIG. 4 shows a configuration example of a 5-bit, 1-stage resistive voltage dividing type D/A converter. The D/A converter shown in the figure includes a reference resistor group consisting of 25 series-connected reference resistors, and 25 switches for switching positions for applying voltage to these resistors. Reference voltages VrefHigh and VrefLow providing a full-scale voltage are applied across this reference resistor group. Based on each of 25 binary codes obtained by decoding a digital input signal via a decoder circuit, not shown, the corresponding one of the switches is selected, whereby a divided analog voltage is outputted to a downstream output amplifier.
As seen from FIG. 4, in the case of the 5-bit resistive voltage dividing type D/A converter, 32 (=25) switches are arranged in parallel, and the outputs of these switches are supplied to the downstream output amplifier (such as an op-amp). The number of switches increases with increasing number of bits, such as 128 switches for a 7-bit configuration, and 512 switches for an 8-bit configuration. When bearing an extremely large load capacitance due to supplied parallel outputs from the switches, the output amplifier becomes hard to drive. Hence, this type of D/A converter is considered unsuitable for high-speed operation. For example, even if a capacitance of each switch with its wiring capacitance equals 10 fF, so large a load capacitance as 128×10 fF=1.28 pF is connected to the input of the op-amp for the 7-bit configuration.
As a scheme for reducing the load capacitance of the resistive voltage dividing type D/A converter, a multi-stage resistive voltage dividing type D/A converter is known. According to this scheme, a plurality of reference resistor groups are provided in a resistive voltage dividing type D/A converter (see, e.g., Non-Patent Reference 1), whereby the load capacitance per stage can be reduced, to achieve higher-speed operation compared with the single-stage resistive voltage dividing scheme. Additionally, its operating principle is based on the resistive voltage dividing scheme, and hence satisfactory monotonously increasing property and differential nonlinearity can be obtained. Furthermore, compared with the single-stage resistive voltage dividing scheme, the design of a decoder becomes simpler, allowing for lower power consumption.
FIG. 5 shows a configuration example of a two-stage multi-stage resistive voltage dividing type D/A converter. In the D/A converter shown in the figure, a reference resistor group circuit includes a first-stage reference resistor group for outputting a rough analog voltage value, and a second-stage reference resistor group for outputting a fine analog voltage value. Of binary data obtained by decoding a digital input signal, a Most Significant Bit (MSB) bit is inputted to the first-stage reference resistor group and a Least Significant Bit (LSB) bit to the second-stage reference resistor group. Furthermore, the reference voltages VrefHigh and VrefLow providing a full-scale voltage are applied across the first-stage reference resistor group.
First, in the first-stage reference resistor group, two voltage taps are selected according to a decoded MSB bit, and in response thereto, the two corresponding analog switches are turned on to extract two different voltages. The two output voltages from the first-stage reference resistor group are applied, as an LSB dynamic range, across the second-stage reference resistor group via inter-stage op-amps.
In the second-stage reference resistor group, two voltage taps are selected according to a decoded LSB bit, and in response thereto, the two corresponding analog switches are turned on to select a finer analog voltage, for output via an op-amp (not shown in the figure) as an analog waveform signal.
FIG. 6A shows the input/output characteristics of the first-stage reference resistor group. Also, FIG. 6B shows the input/output characteristics of the second-stage reference resistor group.
According to the multi-stage resistive voltage dividing scheme, highly accurate D/A conversion output can be obtained, and also the number of reference resistors can be reduced. While 32 (=25) reference resistors are required for the 5-bit D/A converter in FIG. 4, only 12 (=23+22) resistors will do in FIG. 5.
Furthermore, the multi-stage resistive voltage dividing type D/A converter performs conversion by cascading a plurality of resistive voltage dividing D/A converters in multiple stages, whereby the load capacitance at the input of op-amps decreases, permitting high-speed operation. In an example shown in FIG. 5, the first stage is formed of 8 (=23) serially connected reference resistors for a 3-bit MSB configuration, and the second stage is formed of 4 (=22) serially connected reference resistors for a 2-bit LSB configuration, thereby realizing the D/A converter for 5 bits in total. Thus, the load capacitance of the op-amps is suppressed to a value not greater than the total load capacitance of eight switches. If the sum of a capacitance of each switch and its wiring capacitance equals 10 fF, a capacitance connected to the input of the op-amps is approximately 8×10 fF=80fF, which is a marked reduction compared with that in the circuit configuration example shown in FIG. 4. Furthermore, according to the multi-stage resistive voltage dividing scheme, the configuration of the decoder, not shown, can be greatly simplified, allowing for lower power consumption.
The multi-stage resistive voltage dividing type D/A converter addresses a shortcoming that its D/A conversion characteristics is degraded by the offset voltage Voffset of the inter-stage op-amps. When the reference voltage Vref, i.e., the dynamic range of the D/A converter is sufficiently large, and when the voltage range ΔV per LSB is large with respect to the offset voltage Voffset of the op-amps, the D/A conversion characteristics are not particularly affected.